A multiple-port memory cell, such as a dual-port memory cell, includes at least two access ports. Each access port includes a data line or a pair of data lines configured to carry the data read from or written into the memory cell. In various situations, the data lines of both access ports are kept at a logical high voltage level by corresponding clamping circuits. In some configurations, the clamping circuits are introduced to reduce the disturbance to the memory cell when either of the access ports is under a dummy read operation. A dummy read operation occurs to a particular memory cell when the memory cell is not being accessed, but various signals cause the memory cell to be in a read-like condition, such as when a word line is activated to access another memory cell of the same row.